diff --git a/angr/engines/vex/irop.py b/angr/engines/vex/irop.py
index 3093909c..7f2f1f75 100644
--- a/angr/engines/vex/irop.py
+++ b/angr/engines/vex/irop.py
@@ -97,6 +97,8 @@ explicit_attrs = {
     'Iop_V256to64_3': { 'generic_name': 'unpack', 'to_size': 64, },
     'Iop_V256toV128_0': { 'generic_name': 'unpack', 'to_size': 128, },
     'Iop_V256toV128_1': { 'generic_name': 'unpack', 'to_size': 128, },
+    'Iop_MulHi16Sx16': { 'generic_name': 'mulhi' },
+    'Iop_Perm8x8': { 'generic_name': 'perm', 'to_size': 64 },
 }
 
 for _vec_lanewidth in (8, 16, 32, 64):
@@ -854,6 +856,20 @@ class SimIROp(object):
     def _op_Iop_V256toV128_0(self, args): return args[0][127:0]
     def _op_Iop_V256toV128_1(self, args): return args[0][255:128]
 
+    def _op_Iop_Perm8x8(self, args):
+        chopped_arg0 = [claripy.Extract((i + 1) * 8 - 1, i * 8, args[0]) for i in range(8)]
+        chopped_arg1 = (claripy.Extract((i + 1) * 8 - 1, i * 8, args[1]) for i in reversed(range(8)))
+        return claripy.Concat(*(chopped_arg0[j] for i in chopped_arg1 for j in range(8) if ((i&7)==j).is_true()))
+
+    def _op_Iop_MulHi16Sx16(self, args):
+        chopped_args = ([claripy.Extract((i + 1) * 16 - 1, i * 16, a) for a in args]
+                        for i in reversed(range(16)))
+        def mulhi(a,b):
+          a = claripy.SignExt(16,a)
+          b = claripy.SignExt(16,b)
+          return claripy.Extract(31,16,a*b)
+        return claripy.Concat(*(mulhi(a,b) for a,b in chopped_args))
+
     def _op_Iop_QNarrowBin16Sto8Ux16(self, args):
         """
         PACKUSWB Pack with Unsigned Saturation.Two 128 bits operands version.